As the degree of integration of integrated circuit devices continues to increase and the size and scale of devices correspondingly decreases, devices become more delicate in structure and more susceptible to damage during manufacturing. It is a well known problem that as wafer scales decrease in size, circuit yields in terms of the number of usable dies per wafer correspondingly decrease due to various problems associated with the quality of the silicon substrate, the level of cleanliness in the processing plant and other factors. Meanwhile, demand for higher yields resulting from economic pressure is increasing.
One particularly troublesome yield-impacting problem is associated with the bonding of the finished die to a packaging substrate. Such a packaging substrate allows interconnects to be made between the product, represented as a raw die, and an external bonding pad, chip carrier, wire bond, or the like, such that the die or chip can be converted into a useful package that can be soldered or otherwise fixed onto a circuit board, or into a circuit or device.
In a typical post device fabrication process, an interconnect structure is etched during a backside process to form interconnections to the device from the backside such that metal or doped polysilicon can be used to make a connection between the device and the packaging. Disadvantages associated with the conventional processing become immediately apparent in the form of potential damage to the device by, inter alia, the heat associated with the etching and control factors leading to etching beyond the interconnect channel boundary and into the device, and other anomalies. In response to such challenges, some techniques have been proposed that involve various approaches to minimize the contact with delicate device structures once they are in place.
For example, in the above-identified International Application No. PCT/SG2009/000164, an architecture is disclosed wherein interconnect structures are formed on a front side of a wafer before a device is fabricated. The structures are filled with a polysilicon, portions of which are exposed during a backside process such as chemical mechanical polishing or the like. It can be appreciated that the polysilicon structures may have disadvantages in connection with certain applications in that the resistivity of the doped polysilicon can be difficult to control leading to uneven and generally higher resistivity. Such higher resistivity is undesirable for use with certain kinds of lines including power lines, lines having a relatively long span, high frequency lines or other critical signal lines or the like. While Viswanadam teaches that a metal layer may be applied during front side processing while the interconnect structures are formed, there may be limitations associated with such structures formed from a front side process. It is known that differences in the respective coefficients of thermal expansion for a metal structure as compared to a silicon or polysilicon structure can cause problems such as cracking during thermal cycles, which can lead to device failure.
Consequently, in view of the above described and other disadvantages, it has become desirable to successfully perform processing to form interconnect structures such as through vias while overcoming the problems of the art. Examples of conventional processing include the formation of annular metal through vias and the like as described in greater detail herein below. For example, with reference to FIG. 1A, a series of steps associated with the formation of an annular metal through via, such as that described in “A CMOS-compatible Process for Fabricating Electrical Through-vias in Silicon” by P. S. Andry, et al., 2006 Electronic Components and Technology Conference, pp. 832 (hereinafter “Andry”), is shown. It is important to note that in Andry, an annular metal through via is formed by front side fill processing. After front side etching of an annular cylindrical shape to constitute the via, a thermally grown oxide can be used for insulation. After etching, a conductive material is deposited so as to completely fill the insulated via. The conductive materials described in Andry include Cu formed by electrodeposition and tungsten formed by CVD. The wafer can then be thinned and back side processed to expose the vias. It should be noted that the annular conductor via structure benefits from, for example, a silicon core thermal expansion coefficient-matched with the metal and thus results in improved mechanical performance.
In FIG. 1B, a variant described in Andry is shown that includes a core conductor process whereby the annular cylinder is insulated with a thermal grown oxide as described herein above. However, rather than being filled with metal, the annular cylinder is filled with undoped polysilicon and polished and devices and other structures can be added in a manner similar to more conventional processes where vias are added in a final step. The wafer is thinned, and back side patterned. The silicon core is then etched away and replaced with a partial skin of electroplated copper.
In still another conventional process, as described in “High Density Through Wafer Via Technology” by Tomas Bauer, NSTI-Nanotech 2007, Vol. 3, 2007 (www.nsti.org, ISBN 1420061844), pp. 116-119 (hereinafter “Bauer”), a via “plug” can be formed in a low resistivity silicon wafer by laterally isolating a section of the wafer by forming a narrow closed loop trench, on the order of 10 μm to 15 μm, and filling the trench with an isolating material. The resulting isolated plug is then used as the via. A deep reactive ion etching (DRIE) process can be used for trench formation as illustrated in FIG. 10. Various problems arise in connection with plug formation. For example, such a process can be intrinsically wasteful in that the low resistivity material is generally more expensive than insulating material; the unused portion of the low resistivity substrate not used for the via may be considered waste unless used for other conducting applications. Further, it is well appreciated in the art that DRIE processes are relatively expensive compared to other etching processes such as wet etching or the like. Therefore, the necessity of using a DRIE process is more expensive and still further gives rise to the possibility that the plug will become unseated if the etch is too deep resulting in lower yields. Still further, it is not clear whether the scale of the process shown in 1C is reducible to higher or lower scales without additional difficulties.
Such conventional methods are disadvantageous in that they involve front side processing which complicates device formation and attachment; are typically more expensive due to the requirement for more critical processing; and still do not provide for a high degree of control of the resistivity of the via depending on the application. Therefore, there is a need for a method of providing interconnect structures that allows for controlled resistivity, particularly low resistivity.